1. Field of the Invention
The present invention relates to a semiconductor device having an embedded array, a manufacturing method therefor and a storage medium having a program for use in the method.
2. Description of the Related Art
Reduction in power consumption and shortening of development period are required for semiconductor circuits.
A normal-cell design method has a strong point of reducing power consumption in a circuit by designing a cell as small as possible, but together with a fault of an extended design period.
On the other hand, when a circuit is designed using an embedded array in which a plurality of basic cells are arranged in a matrix, there arises an advantage of shortening development period, but in company with weak points of increase in chip area and power consumption, compared with a case where the normal-cell method is applied.
In such a manner, reduction in power consumption and shortening of development period conflict with each other, although both are required to be met.
In the Examined Japanese Patent Application bearing Publication No. Hei 8-1948, there is disclosed a process of designing a semiconductor integrated circuit with using a hard macro cell 1 shown in FIG. 32, in a case where an input 2 and an output 3 is both out of use as a result. An line 5 between the input 2 and a branching point 4 is removed, and further a line 7 between the output 3 and an output end of a block 6 is removed, the block 6, all of whose output end are out of use after the removal of the line 7, is then removed, and a line 9 between an input end of the block 6 and a branch point 8, which is out of use by removal of the block 6, is finally removed. With such a series of removals, a hard macro cell 1A as shown in FIG. 33 can be obtained.
Power consumption of the circuit is reduced by removal of the unnecessary block. Further, capacitance of net is decreased by the sum of capacitance of the removed lines and input capacitance of the input end of the removed block as a result of removal of the unnecessary block and the lines out of use, which contributes to shorten signal propagation delay time.
In this method, however, a hard macro cell with versatile applications is prepared in advance, and circuit blocks and lines, which come to be out of use according to specifications of a selected application, are deleted. Therefore, this method cannot be applied to a case where blocks and lines having no redundancy are formed with adopting an embedded array.
Accordingly, it is an object of the present invention to provide a semiconductor device having an embedded array, a manufacturing method therefor and a storage medium having a program for use in the method, all of which enable reduction in power consumption by removing an unnecessary area of a transistor included in the embedded array, although a slight extension of a development period has to be overlooked.
In the present invention, there is provided a semiconductor device having an embedded array, the embedded array having basic cells arranged in a matrix, wherein a basic cell has an impurity region part of which is removed, the part corresponding with a missing contact hole.
With the present invention, capacitance of an impurity region itself partly removed and parasitic capacitance between the impurity region and a line thereover are decreased compared with a prior art case corresponding thereto, whereby not only is power consumption reduced, but a signal propagation delay time is shortened, so that an operating speed of a basic cell is improved.
Other aspects, objects, and the advantages of the present invention will become apparent from the following detailed description taken in connection with the accompanying drawings.